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Freescale Semiconductor Technical Data
Document Number: MC33884 Rev. 4.0, 11/2006
Switch Monitor Interface
The 33884 Switch Monitor Interface is a monolithic silicon integrated circuit (IC) to perform switch monitoring functions. The device provides efficient interface between electrical switches and low voltage microprocessors. The 33884 supplies switch contact pull-up and pull down current while monitoring the input voltage level. All inputs are protected for transients when implemented with an appropriate static discharge capacitor used on the inputs. There are four modes of operation: Sleep, Normal, Polling, and Polling + INT Timer. The Polling and Timer modes are similar, except the Timer mode has the addition of an interrupt that is sent to the microprocessor if a switch is sensed closed, or upon the internal interrupt timer times out. An interrupt is ultimately sent to the microprocessor. All modes of operation are easily programmed via the Serial Peripheral Interface (SPI) control. Features
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SWITCH MONITOR INTERFACE
DW SUFFIX EG (PB-FREE) SUFFIX 98ASB42344B 24-PIN SOICW
* Full Operation with 7.0 V < VPWR < 26 V, Limited Operation with ORDERING INFORMATION 5.5 V < VPWR < 7.0 V Temperature * Input Voltage Range: -14 V to 40 V Device Package Range (TA) * Interface Directly to Microprocessors Using SPI Protocol * Wake Up on Change of Monitored Switch Status MC33884DW/R2 -40C to 105C 24 SOICW * Programmable Wetting Current MCZ33884EG/R2 * Four Switch-to-Ground Switches * Six (Fixed Function) Inputs Monitoring Six Switch-to-Ground Switches * Two (Fixed Function) Inputs Monitoring Two Switch-to-Battery Switches * Quiescent Current in Sleep Mode < 10 A * Reset Input Defaults the Device to Sleep Mode * Pb-Free Packaging Designated by Suffix Code EG
VPWR
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2 VPWR Sense Inputs SB1 SB2 SP1 SP2 SP3 SP4 SG1 SG2 SG3 SG4 SG5 SG6 VPWR VDD CS SI SO SCLK INT RESET GND VBG SYNC MASL
VDD MCU VDD CS MOSI MISO CLK INT RESET GND
4 GND / VPWR Sense Inputs
6 GND Sense Inputs
Figure 1. 33884 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products.
(c) Freescale Semiconductor, Inc., 2006. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
SP1 SP2 SP3 SP4
Switch-to-Ground and Switch-to-Battery Sense Inputs (x4)
Programmable Input Blocks (1-4)
Metallic or Non-metallic Enable or Disable Input Block (Tri-State)
SG1 SG2 SG3 SG4 SG5 SG6
Switch-to-Ground Sense Inputs (x6)
Fixed Input Blocks GND (1-6)
Switch-Ground, Metallic or Nonmetallic, Enable or Disable FIB (Tri-State)
SPI Decode
PIB Configure, FIB/PIB Tri-State FIB/PIB Metallic
SB1 SB2
Switch-to-Battery Sense Inputs (x2)
Fixed Input Blocks Battery (1-2)
Switch-Batt, Metallic or Non-Metallic, Enable or Disable FIB (Tri-State)
SPI Interface
CS SI SO SCLK
SPI Encode
Mode Switch Status Quiescent Current Control
VDD VPWR VSS
VDD, V+ Distribution
(To all input blocks)
Mode Control
Normal, Polling, Sleep Polling Mode
INT Oscillator
Wake Up Slave Sync
VBG
RST
SYNC MASL
Master/Slave Select
Figure 2. 33884 Simplified Block Diagram
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PIN CONNECTIONS
PIN CONNECTIONS
VDD SO SI SP1 SG1 SG2 SG3 SB1 SP2 MASL VPWR VSS
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
SCLK CS VBG SP4 SG6 SG5 SG4 SB2 SP3 INT SYNC RST
Figure 3. 33884 Pin Connections Table 1. 33884 Pin Definitions
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Pin Name VDD SO SI SP1 SG1 SG2 SG3 SB1 SP2 MASL VPWR VSS RST SYNC INT SP3 SB2 SG4 SG5 SG6 SP4 VBG Formal Name Voltage Power Serial Output Serial Input Switch Input One Switch-to-Ground Inputs One Switch-to-Ground Inputs Two Switch-to-Ground Inputs Three Switch-to Battery One Switch Input Two Master/Slave Voltage Power Voltage SS Reset Synchronization Interrupt Switch Input Three Switch-to-Battery Two Switch-to-Ground Inputs Four Switch-to-Ground Inputs Five Switch-to-Ground Inputs Four Switch Input One Bandgap Voltage This pin is 5.0 V logic supply. This pin is the SPI data out. This pin provides data input. This pin senses inputs programmed to read switch-to-ground (battery) supply contacts. This pin is one of six and are switch-to-ground inputs only. This pin is one of six and are switch-to-ground inputs only. This pin is one of six and are switch-to-ground inputs only. This pin is one of two, and senses inputs only. This pin senses inputs programmed to read switch-to-ground (battery) supply contacts. This pin identifies which device will be master and which will be slave. This pin is the power source. This pin is a ground. This pin is active low reset input to the device. This pin is used by the slave IC during the Polling mode. This pin is an interrupt output from the device. This pin senses inputs programmed to read switch-to-ground (battery) supply contacts. This pin is one of two, and senses inputs only. This pin is one of six and are switch-to-ground inputs only. This pin is one of six and are switch-to-ground inputs only. This pin is one of six and are switch-to-ground inputs only. This pin senses inputs programmed to read switch-to-ground (battery) supply contacts. This pin.... Definitions
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PIN CONNECTIONS
Table 1. 33884 Pin Definitions
Pin Number 23 24 Pin Name CS SCLK Formal Name Chip Select Serial Clock Definitions This pin is transmits communication to the device. This pin clocks the internal 16-bit Shift register of the device.
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted.
Rating Power Supply Voltage CS, SI, SO, SCLK, RST, MASL, SYNC, INT VPWR Supply Voltage (1) Switch Input Voltage Range Recommended Frequency of SPI Operation ESD Voltage
(2) (1)
Symbol VDD
Value -0.3 to 7.0
Unit VDC
VPWR VSI fSPI
-16 to 50 -14 to 40 3.0
VDC VDC MHz V
Human Body Model (3) (4) Machine Model (3) (5) Storage Temperature Operating Case Temperature Operating Junction Temperature Peak Package Reflow Temperature During Reflow Thermal Resistance (Junction-to-Ambient)
(6) (7)
VESD1 VESD2 TSTG TC TJ , TPPRT PJ-A
4000 200 -55 to 150 -40 to 105 -40 to 150 Note 7. 107 C C C C C/W
Notes 1 Exceeding these limits may cause malfunction or permanent damage to the device. 2 ESD data available upon request. 3 ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ) and ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ). 4 5 6 7. All pins are tested individually. 1 kV on VPWR and VDD when connected together. See page three. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics Characteristics noted under conditions 4.75 V VDD 5.25 V, 9.0 V VPWR 16 V, -40C TC 105C, unless otherwise noted. Typical values, where applicable, reflect the parameter's approximate average value with VPWR = 13 V, TA = 25C.)
Characteristic POWER INPUT Supply Voltage Range Quasi-Functional (8) Fully Operational Supply Current Normal Mode (IDD + IPWR) (All switches open) Supply Current Sleep State (IDD(SS) + IPWR(ON)) Supply Current Periodic Mode (Polling at 30-50 ms period) (All switches open) Logic Supply Voltage Bandgap Voltage Output Pin (Tested with 130 k 0.1% resistor) Switch Input Pulse Wetting Current Switch to Battery Switch Input Pulse Wetting Current Switch to Ground Switch Input Sustain Current Switch to Battery Switch Input Sustain Current Switch to Ground Switch Input Tri-State Input Current Switch Input Switch Detection Threshold Switch Input Switch Input Voltage Range VDD VBG
IW(BAT) IW(GND) IS(BAT)
Symbol
Min
Typ
Max
Unit
V VPWR(QF) VPWR(FO) IPWR(ON) I(SS) 5.5 7.0 -- -- -- 4.75 1.18 7.5 -7.5 0.4 -0.4 -10 3.25 -14 100 2.0 26 -- 1.26 14 -14 0.75 -0.75 -- 3.75 -- -- 7.0 26 300 10 -- 5.25 1.4 25 -25 1.25 -1.25 10 4.75 40 A A A V V mA mA mA mA A V V
IS(GND) IT(SWT) ITH VIN
Notes 8 SPI inputs and outputs are operational. Fault reporting may not be fully operational within this voltage range. See page five.
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 4.75 V VDD 5.25 V, 9.0 V VPWR 16 V, -40C TC 105C, unless otherwise noted. Typical values, where applicable, reflect the approximate parameter mean with VPWR = 13 V, TA = 25C under nominal conditions, unless otherwise noted.
Characteristic POWER INPUT TIMING Pulse Wetting Current Duration Interrupt Delay Time SCLK Frequency vs. SO Load Capacitance 200 pF 160 pF 120 pF DIGITAL INTERFACE TIMING Input Logic Voltage Thresholds (13) SO High State Output Voltage (IOH = 1 mA) SO Low State Output Voltage (IOL = 1 mA) SO Tri-State Leakage Current (CS = 0.7 VDD, VSO = 0 to VDD) SI Pull Down Current (SI = VDD) SCLK Input Current (0 V = VDD) CS Pull-Up Current (CS = 0 V) RST Pull Down Current (RST = 0 V) INT Low State Output Voltage (IOL = 0.5 mA) Input Capacitance on SCLK, SI, Tri-State, SO, CS Falling Edge of CS to Rising Edge of SCLK
(13) (13)
Symbol
Min
Typ
Max
Unit
tPULSE tINT(DELAY)
3.0 2.5
34 --
43 13
ms
ms
fSCLK
3.2 3.5 4.0
-- -- --
-- -- --
MHz
VIN(LOGIC) VOH(SO) VOL(SO) IT(SO) ISI ISCLK ICS IRST VOL(INT) CIN tLEAD tLAG tSU2 tH2 tSU1 tH1 tR(SO) tF(SO) tR(SI) tF(SI) tSO(EN)
0.2 x VDD 3.5 -- -40 5.0 -10 -25 5.0 -- -- -- -- -- -- 90 90 --
-- -- -- -- -- -- -- -- -- -- 100 -- 25 25 125 125 30
0.7 x VDD -- 0.4 40 35 10 -5.0 35 0.4 20 140 50 45 45 -- -- 50
V V V A A A A A V pF ns ns ns ns ns ns ns
(Required set-up time)
Falling Edge of SCLK to Rising Edge of CS (Required set-up time) SI to Rising Edge of SCLK (Required set-up time) Rising Edge of SCLK to SI (Required hold time) SO to Rising Edge of SCLK Rising Edge of SCLK to Falling Edge of SO (Hold time) SO Rise Time, SO Fall Time (CL = 200 pF) SI, CS, SCLK Incoming Signal Rise Time (13) SI, CS, SCLK Incoming Signal Fall Time (13) Time from Falling Edge of CS to SO Low Impedance (13) Notes 9 10 11 12
-- -- --
-- -- 80
50 50 110
ns ns ns
Upper and lower logic threshold voltage levels apply to SI, CS, SCLK, RST, SYNC, MASL. See page five. This parameter is guaranteed by design, however, it has not been production tested. Rise and fall time for incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. Time required for output states data to be available at SO pin.
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 4.75 V VDD 5.25 V, 9.0 V VPWR 16 V, -40C TC 105C, unless otherwise noted. Typical values, where applicable, reflect the approximate parameter mean with VPWR = 13 V, TA = 25C under nominal conditions, unless otherwise noted.
Characteristic Time from Rising Edge of CS to SO High Impedance (13) Time from Falling Edge of SCLK to SO Data Valid (14) Recovery Time for Sequential Transfers Symbol tSO(DIS) tVALID tREC Min -- -- -- Typ 80 65 100 Max 110 105 120 Unit ns ns ns
Notes 13 Time required for output states data to be terminated at SO pin. 14 Time required to obtain valid data out from SO following the falling edge of SCLK.
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FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33884 is a monolithic integrated circuit designed to interface between external electrical system switches and low voltage microprocessors via a Serial Peripheral Interface (SPI). The 33884 monitors the OPEN/CLOSED status of multiple external switches used in a system. The 33884 features four programmable Switch-to-Ground or Battery sense inputs, 6 Switch-to-Ground sense inputs, 2 Switch-toBattery sense inputs, programmable Wake up Timer, programmable Interrupt Timer, and programmable wetting current settings. All inputs are protected for ESD transients when implemented with the appropriate ESD capacitor. There are numerous applications for this device in aircraft, aerospace, robotic, process & control, automotive, and security systems. Potential applications exist where switch status verification for safety, fault tolerant operation, or process control function purposes are critical. The 33884 has four modes of operation: Sleep, Normal, Polling, and Polling + INT Timer. The 33884 is designed to provide a robust interface between system switch contacts and a microprocessor. Each 33884 input provides the switch contact with high levels of wetting current during switch closure. After the input switch has been closed for 20 ms, the wetting current is reduced, hence reducing power dissipation in the IC. The response to a SPI command will always return Switch Status, Master/ Slave, INT Flag, and Mode settings. The following section describes the programming modes and features of the 33884.
MICROPROCESSOR INTERFACE
The M33884 directly interfaces to 3.3 or 5.0 V MCU. SPI serial clock frequencies in excess of 5.0 MHz may be used for programming and reading switch input status. Figure 4 shows the configuration between an MCU and one 33884.
MC68HCXX Microcontroller
MOSI
16 Bit Shift Register
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SI
16 Bit Shift Register
MISO SCLK
Receive Buffer Parallel Ports
SO
To Logic
RST CS INT INT
Figure 4. SPI Interface with Microprocessor The 33884, though originally designed for automotive use, is very useful in a variety of other applications, i.e., computer, telecommunications, and industrial fields. It is parametrically specified over an input battery/supply voltage of 9.0 to 16.0 V but is designed to operate over a considerably wider range of 5.5 to 26.5 V. Two or more 33884 devices may be used in a module system when implemented in a parallel or serial configuration. Figure 5 and Figure 6 show the parallel and serial configurations respectively. When using the Serial configuration, 32 clock cycles are required for a complete transfer of data to the 33884.
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FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION
MC68HCXX Microcontroller
MOSI
16 Bit Shift Register
MC68HCXX Microcontroller
SI MOSI SI SO SCLK CS RST INT
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MISO SO SCLK CS RST INT
16 Bit Shift Register
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MISO SCLK
Parallel Ports
SCLK
Parallel Ports
INT
INT
SI
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SO SCLK CS RST INT
SI SO
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SCLK CS RST INT
Figure 5. SPI Parallel Interface with Microprocessor
Figure 6. SPI Serial Interface with Microprocessor
FUNCTIONAL PIN DESCRIPTION CHIP SELECT (CS)
The MCU system selects the 33884 to receive its communication through the Chip Select (CS) pin. With the CS in a logic low state, command words may be sent to the 33884 via the Serial Input (SI) pin. Switch status is received by the MCU via Serial Output (SO) pin. The falling edge of CS enables the SO output, latches the state of the Interrupt (INT) pin, Operating mode and the state of the external switch inputs. The rising edge of CS disables the SO driver, resets the INT pin to logic [1], activates the received command word, and allows the 33884 to act upon new data obtained from switch inputs. To avoid any spurious data, it is essential the high-to-low and low-to-high transition of the CS signal occur only when System Clock (SCLK) is in a logic low state. Internal to the 33884 is an active pull-up on CS pin.
SERIAL INPUT (SI)
This Serial Input (SI) pin is used for serial instruction data input. SI information is latched into the Input register on the rising edge of SCLK. A logic high state present at SI when SCLK rises, programs a logic [1] into the command word on rising edge of the CS signal. To program a complete word, 16 bits of information must be entered into the 33884. Internal to the IC is an active pull down on the SI pin.
SERIAL OUTPUT (SO)
The Serial Output (SO) pin is the output from the Shift register. The SO pin remains Tri-Stated until the CS pin transitions to a logic low state. All open switches are reported as logic [0], all closed switches are reported as logic [1]. The negative transition of CS will make status bit 15 available on SO. Each successive negative clock makes the next status bit available. The SI/SO shifting of the data follows a first-infirst-out protocol with both input and output words transferring the most significant bit (MSB) first.
SYSTEM CLOCK (SCLK)
The System Clock (SCLK) pin clocks the internal 16-bit Shift register. The Serial Input (SI) data is latched into the Input Shift register on the rising edge of SCLK signal. The Serial Output (SO) pin shifts the switch status bits out on the falling edge of SCLK. False clocking of the Shift register must be avoided to guarantee validity of data. It is essential the SCLK pin be in a logic low state whenever CS makes any transition. For this reason it is recommended, though not necessary, the SCLK pin be commanded to a low logic state as long as the device is not accessed (CS in logic high state). When the CS is in a logic high state, any signal on the SCLK and SI pin will be ignored and the SO pin is Tri-Stated (high impedance).
MASTER/SLAVE (MASL)
The Master/Slave (MASL) pin is required when multiple 33884 devices are used in one module. The MASL identifies which device will be the master or slave. MASL identification is used during the Polling mode. In the Polling mode, the master device has it's internal oscillator running while the Slave device oscillator is shutdown. While polling, the master device wakes the slave via the Synchronization (SYNC) pin. This feature provides minimal quiescent from the voltage power (VPWR) and voltage digital drain (VDD) pins.
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FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION
SYNCHRONIZATION (SYNC)
The Synchronization (SYNC) input is used by the slave IC during the Polling mode. The SYNC allows multiple 33884 ICs to poll the multiple inputs concurrently. The master controls the polling period. The slave is allowed to shut down it's oscillator, thereby conserving current. When the slave receives the SYNC signal from the master, the slave starts the internal oscillator and reads the switch inputs.
voltage on VPWR is 40 V. All wetting currents and sustain currents are derived from VPWR.
SWITCH PINS (SP1 : SP4)
The 33884 has four programmable switch sense inputs (SP1- P4) to read switch-to-ground or switch-to-battery/ supply contacts. Transient battery/supply voltages greater than 40 V must be clamped by an external device. Surface mount 0805 MOVs and transient voltage suppressors (TVS) are available in SOT-23 packages. The sensed input is compared with an internal 4.0 V reference. When programmed to sense switch-to-battery, sensed voltages greater than 4.0 V are interpreted as a CLOSED switch, while sensed voltages less than 4.0 V are interpreted as an OPEN switch. The opposite holds true when inputs are programmed to sense switch-to-ground. Further programming can set the wetting currents or make the inputs Tri-State. Programming methods are provided in the following section.
INTERRUPT (INT)
The Interrupt (INT) pin is an interrupt output from the 33884. The INT pin is an open drain output with an internal pull-up. In the Normal mode, a switch state change triggers the INT pin. The INT pin and INT bit (flag) are latched on the falling edge of CS. This procedure determines the interrupt origin. The flag INT bit in the SPI word is the inverse of the INT pin. The INT pin is cleared on the rising edge of CS. The INT pin is active only during the ON time (when sink and source currents are active) in the Polling mode.
SWITCH-TO-BATTERY (SB1 AND SB2) RESET (RST)
The Reset (RST) pin is active low reset input to the 33884. When asserted, the 33884 will reset all internal registers, timers, and enters a Sleep mode (with all switch inputs in a Tri-State condition). Only an MCU SPI command word will wake the 33884 from a Sleep state. The RST pin may be controlled directly from a general purpose input/output (GPIO) pin or from a system/MCU reset. The two Switch-to-Battery (SB) pins sense inputs only. Transient battery/supply voltages greater than 40 V must be clamped by an external device. Surface mount 0805 MOVs and transient voltage suppressors (TVS) are available in SOT-23 packages. The sensed input is compared with an internal 4.0 V reference. Voltages greater than 4.0 V are interpreted as a CLOSED switch, while sensed voltages less than 4.0 V are interpreted as an OPEN switch. Programming can set wetting currents or Tri-State the input. Programming methods are provided in the following section.
BANDGAP VOLTAGE (VBG)
The Bandgap Voltage (VBG) pin requires a 130 k to ground for standard wetting and sustain currents. The device is tested with a 0.1 percent value, but a standard 1.0 percent could be used to function properly.
SWITCH-TO-GROUND (SG1 : SG6)
The six Switch-to-Ground (SG) pins are inputs only. The input is compared with the internal 4.0 V reference. Voltages greater than 4.0 volts are interpreted as an OPEN switch. Voltages less than 4.0 V are interpreted as a CLOSED switch. Programming can set the wetting currents or Tri-State the input. Programming methods are provided in the following section.
VOLTAGE POWER (VPWR)
The Voltage Power (VPWR) pin is battery/supply source pin for the 33884. The VPWR pin requires external reverse battery/supply and transient protection. Maximum input
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES POWER-UP
On initial power-up all 33884 registers are cleared and the device enters the Sleep mode. To exit the Sleep mode, a valid command word is required to be received from the microprocessor. during sensed switch OFF periods. The Polling mode allows reduction of quiescent current by disabling sink and source currents during switch OFF periods. 3. The Polling + INT Timer mode of operation is similar to the Polling mode above, except with the addition of an interrupt being sent to the microprocessor if a switch is sensed CLOSED, or upon the internal interrupt timer timing out. An interrupt is always ultimately sent to the microprocessor in this mode. The microprocessor can be programmed to read, or ignore the reported switch status while receiving the interrupt. If a switch is sensed CLOSED, operation automatically reverts to the Normal mode. If all switches are sensed OPEN, and the wake up timer (INT Timer) times out, the 33884 continues to operate in the Polling + INT Timer mode. The wake up timer duration may be set much longer than the polling time. The command also programs the SP1 to SP4 sense inputs (switch-to-battery logic [1] or switch-to-ground logic[0]). Please refer to Table 17.
SLEEP COMMAND
Sleep mode can be entered by a SPI Sleep command or asserting the RST pin. In Sleep mode all inputs are Tri-State and all internal active pull up and pull down currents are disabled. Sleep mode reduces the current drain to a quiescent current level of 10 A and disables the IC. Sleep mode provides lowest quiescent current for the IC. Exit from sleep mode requires a valid SPI RUN, TRI-STATE, or METALLIC command.
RUN COMMAND
The Run command places the IC in one of three operating modes: 1. This is the normal operating mode of the 33884. In Normal mode the status of the input switches are latched on falling edge of CS and data is returned to the MCU via SPI. All programmed combinations of source and sink currents, used for sensing purposes, are always active in this mode. While in the Normal mode, an interrupt is generated and sent to the microprocessor whenever an external switch changes its OPEN or CLOSED state. Prior to a switch closing, the 33884 sources 0.75 mA of sustain current. When the voltage at the input crosses the comparator threshold, 14 mA of current is allowed to flow. The 14 mA wetting current shuts off after a 20 ms timer expires. 2. The Polling mode reads a switch status periodically, interrupting the microprocessor only when an external switch is sensed as being CLOSED. When the 33884 senses all external switches to be OPEN, the Polling mode of operation continues. When a switch is sensed CLOSED, an interrupt is sent to the microprocessor, transferring it's operational mode to the Normal mode. The Polling mode provides a reduction in quiescent current by turning OFF all source and sink currents
TRI-STATE COMMAND
A Tri-State command places all switch inputs into Tri-State position. All comparators on input are disabled in this mode. The device will return logic [0] for the switch status.
SPI PROGRAMMING
The 33884 uses the SPI in full duplex synchronous slave mode for communication with the microprocessor. The 33884 is programmed via a 16-bit word command from the MCU. The word is sent to the device with the MSB first. The command word sent to the 33884 sets the mode of operation in the device. Returning data received from the 33884 is the status of the sensed input switch on the falling edge of CS. Sixteen clock periods are required for each transmission to be valid. After the 16 clocks, CS is returned to the inactive state (logic [1]), command words are no longer accepted into SI, and the SO pin is Tri-Stated. The response to a SPI command returns status based on previous command word. This previous command could be a hardware reset as well as any of the other commands discussed in this section.
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS PROGRAMMING AND CONFIGURATION DESCRIPTION
SPI Commands from Microcontroller / Command Protocol (Data into SI) Table 5. SPI Command Protocol
MSB Command Sleep (Default) Run Tri-State Metallic IC Test Mode Reset Values: Run Register Tri-State Register Metallic Register -- -- -- -- -- -- -- -- U 0 U 0 U 0 U 0 U 0 U 0 U 0 U 0 U 0 U 0 U 0 U 0 16 0 0 0 0 1 15 0 0 0 1 x 14 0 0 1 0 x 13 0 1 1 1 x 12 x 11 x 10 x ST3 TG4 MG4 x 9 x ST2 TG3 MG3 x 8 x ST1 TG2 MG2 x 7 x -- TG1 MG1 x 6 x WT2 TP4 MP4 x 5 x WT1 TP3 MP3 x 4 x CP4 TP2 MP2 x 3 x CP3 TP1 MP1 x 2 x CP2 TB2 MB2 x LSB 1 x CP1 TB1 MB1 x
MOD2 MOD1 TG6 MG6 x TG5 MG5 x
--
--
--
--
U
U
U
U
U
U
U
U
U
U
U
U
U =Unknown value coming out of Sleep mode. It be must configured with Run and Metallic commands. Note: the remaining combinations of bits [16;13] are non-functional (0010. 0100. 0110. 0111). MOD[2:1] = Operating mode CP[4:1] = Configure programmable switch TG[6:1] = Tri-State switch-to-ground TB[2:1] = Tri-State switch-to-battery
TP[4:1] = Tri-State programmable switch ST[3:1] = Sample OFF time WT[3:1] = Wake up time MG[6:1] = Metallic switch-to-ground MB[2:1] = Metallic switch-to-battery MP[4:1] = Metallic programmable switch
SLEEP COMMAND
The Sleep command places the IC in Sleep mode and essentially turns the part OFF. By definition, a hardware reset sends/keeps the IC in Sleep mode. All inputs are Tri-Stated, Table 6. Sleep Command
MSB Command Sleep (Default) 16 0 15 0 14 0 13 0 12 x 11 x 10 x 9 x
disabling all input blocks and all internal pull-ups/pull downs. Only a SPI command can take the IC out of Sleep mode. Exiting this mode requires a valid Run, Tri-State, or Metallic command.
LSB 8 x 7 x 6 x 5 x 4 x 3 x 2 x 1 x
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
RUN COMMAND
The Run command gives access to all operating modes: Normal, Polling, and Polling + INT Timer. It allows selection Table 7. Run Command
MSB Command Run Reset Values: Run Register -- -- -- -- U U U U 16 0 15 0 14 0 13 1 12 11 10 ST3 9 ST2
of tWAIT and tWAKE, and configures the programmable input blocks. Bit 7 is currently unused. Note that the Run register values are unknown after exiting the Sleep mode.
LSB 8 ST1 7 -- 6 WT2 5 WT1 4 CP4 3 CP3 2 CP2 1 CP1
MOD2 MOD1
U
U
U
U
U
U
U
U
U = Unknown value coming out of Sleep mode. It must be configured with Run command.
Table 9. Sample OFF Time Prescales
MOD[2:1] OPERATING MODE
In the Run command, the two MOD bits place the device in one of three operating modes: Normal, Polling, and Polling + INT Timer. Table 8. Bit Definition for Run Command
Command: Run (0001) with bits [12:1]
010 Mode Undefined Normal Polling Polling + INT Timer MOD2 0 0 1 1 MOD1 ST[3:1] WT[2:1] CP[4:1] 011 0 1 0 1 xxx xxx ST[3:1] xx xx xx CP[4:1] 100 CP[4:1] 101 CP[4:1] 110 ST[3:1] WT[2:1] CP[4:1] 111 ST[3:1]
Multiplier Selected 5 9 17 25 33 41 49 57
OFF Time, tWAIT (ms) [tDETECT (4.8ms typ) x Multiplier] 15 - 25 30 - 55 60 - 90 100 - 140 145 - 185 195 - 215 220 - 245 250 - 320
ON Time (ms) 5.1 - 6.3 5.1 - 6.3 5.1 - 6.3 5.1 - 6.3 5.1 - 6.3 5.1 - 6.3 5.1 - 6.3 5.1 - 6.3
000 001
ST[3:1] - OFF TIME BETWEEN SAMPLES (TWAIT)
During both Polling modes (with and without INT Timer wake up, MOD2=[1]), these bits select the interval of time (tWAIT) the Input Blocks are turned OFF; switch transitions are not detected during the OFF interval.
WT[2:1] - WAKE UP TIME
These bits allow the device to assert an external interrupt (INT) at the following intervals during Polling mode (MOD2 = MOD1 = 1). Table 10. Wake Up Delay Prescales
WT[2:1] 00 01 10 11 Multiplier Selected 512 + 1 256 + 1 128 + 1 64 + 1 Wake Up Interrupt, tWAIT (ms) [tDETECT (2.8ms typ) x Multiplier] 2400 - 3200 1200 - 1600 600 - 750 290 - 360
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
TRI-STATE COMMAND
This command places an external switch into a Tri-State condition, essentially disconnecting the wetting current (if the switch is metallic) and the sustain current. The internal inputthreshold comparator is still internally connected to its external pin. This command does not change the mode of operation
Note: This configuration may be entered in any of the three valid Operating Modes (see MOD[2:1]) within the Run command. Table 11. Programmable Switch Bit Definition
CPx 0 1 External Switch to: Ground Battery
CP[4:1] - CONFIGURE PROGRAMMABLE SWITCH
Configure the programmable inputs SP[4:1] to detect either an external switch-to-ground (internal current source) or an external switch-to-battery (internal current sink).
(e.g., a Tri-State command received while in the Polling mode leaves the part in that mode). Note: The Tri-State register clears all bits to logic [0] (all inputs in Tri-State) in response to a hardware reset; all inputs also remain in Tri-State after existing the Sleep mode.
Table 12. Tri-State Command
MSB Command Tri-State Reset Values: Run Register -- -- -- -- 0 0 0 0 0 0 0 0 0 0 0 0 16 0 15 0 14 1 13 1 12 TG6 11 TG5 10 TG4 9 TG3 8 TG2 7 TG1 6 TP4 5 TP3 4 TP2 3 TP1 2 TB2 LSB 1 TB1
TG[6:1] = Tri-state switch-to-ground TB[2:1] = Tri-state switch-to-battery TP[4:1] = Tri-state programmable switch
Table 13. Programmable Switch Bit Definition
TGx, TBx, TPx 0 1 Input Configured to: Input Disabled (Default) Input Enabled
METALLIC COMMAND
This command enables the pulsed wetting current for an external metallic switch and disables it for an external nonmetallic switch. This command does not change the mode of operation (e.g., a Metallic command received while in Polling mode leaves the part in that mode). Note that the Run register values are unknown after exiting the Sleep mode.
Table 14. Metallic Command
MSB Command Metallic Reset Values: Run Register -- -- -- -- U U U U U U U U U U U U 16 0 15 1 14 0 13 1 12 MG6 11 MG5 10 MG4 9 MG3 8 MG2 7 MG1 6 MP4 5 MP3 4 MP2 3 MP1 2 MB2 LSB 1 MB1
U = Unknown value coming out of Sleep mode. It must be configured with Run command. MG[6:1] = Metallic switch-to-ground MB[2:1] = Metallic switch-to-battery MP[4:1] = Metallic programmable switch
Table 15. Metallic Switch Bit Definition
MGx, MBx, MPx 0 1 Accept Switch Type: Non-Metallic Metallic (Enable Wetting Current Pulse)
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
TEST MODE
Bit 16 is reserved for placing the device into a special IC Test mode. It is used to confirm various internal functions. Table 16. Test Mode
MSB Command IC Test Mode 16 1 15 x 14 x 13 x 12 x 11 x 10 x 9 x 8 x 7 x 6 x 5 x 4 x 3 x 2 x LSB 1 x
SPI RESPONSES
Response Protocol (Data out of SO). Table 17. SPI Responses
MSB Mode Reset/Sleep Normal Polling Polling + INT Timer 16 0 0 1 1 15 0 1 0 1 14 x MASL MASL MASL 13 x INT x INT 12 x SG6 SG6 SG6 11 x SG5 SG5 SG5 10 x SG4 SG4 SG4 9 x SG3 SG3 SG3 8 x SG2 SG2 SG2 7 x SG1 SG1 SG1 6 x SP4 SP4 SP4 5 x SP3 SP3 SP3 4 x SP2 SP2 SP2 3 x SP1 SP1 SP1 2 x SB2 SB2 SB2 LSB 1 x SB1 SB1 SB1
SG[6:1] = Switch-to-ground flag SB[2:1] = Switch-to-battery flag SP[4:1] = Programmable switch flag
MASL = Master/Slave identification flag INT = External Interrupt flag
RESET/SLEEP
When the Reset (RST) input is active (logic [0]), all internal registers are cleared, thereby placing the device in Sleep mode and upon the RST input returning to the inactive state Table 18. Reset/Sleep
MSB Mode Reset/Sleep 16 0 15 0 14 x 13 x 12 x 11 x 10 x
(logic [1]) the MC33884 remains in Sleep mode. A SPI command, received from the microprocessor, is necessary to command the device out of Sleep mode.
LSB 9 x 8 x 7 x 6 x 5 x 4 x 3 x 2 x 1 x
Note: The SPI response given while sending the command to exit Sleep mode should be ignored due to unknown power-up state.
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
NORMAL AND PERIODIC
Bits [16:15] identify one of the three operating modes: Normal, Polling, and Polling + INT Timer. The remaining bits Table 19. Normal and Periodic
MSB Mode Normal Polling Polling + INT Timer 16 0 1 1 15 1 0 1 14 MASL 13 INT x INT 12 SG6 11 SG5 10 SG4
identify the device as the Master or a Slave, whether the device has an interrupt that has not been cleared, and the state of all the inputs.
LSB 9 SG3 8 SG2 7 SG2 6 SG1 5 SP3 -- -- 4 SP2 3 SP1 -- -- 2 SB2 1 SB1
Note: The SPI response given while sending the command to exit Sleep mode should be ignored due to unknown power-up state.
MASL- MASTER/SLAVE IDENTIFICATION FLAG
This flag is the same as the state of the MASL pin. It provides software identification of the configuration of each IC. Table 20. MASL Bit Definition
MASL 0 1 Device is a: Slave Master
These twelve flags indicate the state of all switch inputs: Table 22. Switch State Bit Definition
SGx, SBx, SPx 0 1 External Switch is: Open Closed Mode Normal Polling Input States Latched: At the moment CS transitions to logic 0
TRI-STATE INT - EXTERNAL INTERRUPT FLAG
This flag identifies this particular IC as the initiator of an external interrupt. It is the inverse of INT. Table 21. MASL Bit Definition
MASL Normal 16 0 -- Polling 1 1 Polling + INT Timer -- 15 1 -- 0 1 -- 14 x -- x x -- 13 0 1 x 0 1 Type of Interrupt Nothing Happened Switch Interrupt -- Nothing Happened Wake up Interrupt 0
All Tri-State inputs have their wetting and sustain currents disabled. By definition, all disabled inputs return the following value for the switch state whenever SPI data is exchanged: Table 23. Tri-State Bit Definition
SGx, SBx, SPx External Switch is: Tri-State
SG[6:1] = Switch-to-ground flag SB[2:1] = Switch-to-battery flag SP[4:1] = Programmable switch flag
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TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
External Switches
VPWR VDD SB1 VPWR
10 nF 0805 100 V 10 nF 0805 100 V
VBAT T VBAT T VBAT T
SB2
10 nF 0805 100 V 10 nF 0805 100 V
VDD
MC68HCXX Microcontroller
10k 0805 MOSI MISO
SP1
33884
SI
10 nF 0805 100 V
16 Bit Shift Register
M S B L S B
VBAT T SP2 VBAT T
10 nF 0805 100 V
SO SCLK
SP3 VBAT T
10 nF 0805 100 V
INT
CS
Parallel Ports
SP4
10 nF 0805 100 V 10 nF 0805 100 V 10 nF 0805 100 V 10 nF 0805 100 V 10 nF 0805 100 V
VBG RESET SG1
130k 0805
SG2
SG3 RST SG4
10k 0805
WDOG LVI RESET Control
SG5
10 nF 0805 100 V 10 nF 0805 100 V
SG6
Master Node
MASL SYNC
VBAT T VBAT T VBAT T
SB1
10 nF 0805 100 V
SYNC
Slave Node
SB2
VPWR
10 nF 0805 100 V
10 nF 0805 100 V
SP1
10 nF 0805 100 V
MC33884
VDD
10 nF 0805 100 V
VBAT T SP2 VBAT T
10 nF 0805 100 V
SI SO SCLK INT CS SP3 RST MASL VBG SP4
VBAT T
10 nF 0805 100 V
10 nF 0805 100 V
130k 0805
Figure 7. Typical Master/Slave Application
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PACKAGING PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the "98A" listed below.
DW SUFFIX EG (Pb-FREE) SUFFIX PLASTIC PACKAGE 98ASB42344B ISSUE F
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REVISION HISTORY
REVISION HISTORY
REVISION 3.0
DATE 6/2006
DESCRIPTION OF CHANGES * * * * * Implemented Revision History page Converted to Freescale format Corrected content to the prevailing form and style Removed MC33884EG/R2, and replaced with MCZ33884EG/R2 in the Ordering Information block Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from Maximum ratings on page 5. Added note with instructions from www.freescale.com.
4.0
11/2006
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MC33884 Rev. 4.0 11/2006

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